In general, a cache is high-speed memory which sits between outer level storage (e.g., disk drive memory) and computerized processing circuitry (e.g., a processor) which stores data into and retrieves data from the outer level storage. When the processing circuitry requires data from the outer level storage, cache circuitry (e.g., a cache controller) moves a copy of the data from the outer level storage into the cache, and the processing circuitry then reads the copy of the data from the cache. If the processing circuitry needs to retrieve the data again and if the copy of the data still resides in the cache, the processing circuitry can simply re-read the copy of the data from the cache (i.e., a cache hit). Similarly, when the processing circuitry stores data to the outer level storage, the processing circuitry writes the data into the cache, and cache circuitry moves a copy of the data into the outer level storage (e.g., the cache circuitry simultaneously writes the data to the outer level storage if the cache is a write-through cache, the cache circuitry writes the data to the outer level storage at a later time if the cache is a copy-back cache, etc.).
Conventionally, the cache circuitry manages data in a location-aware manner. That is, the cache circuitry associates copies of data within the cache with the location, or address, of where the data resides in the outermost level of memory (e.g., disk drive memory). For example, suppose that locations X and Y of the outermost level of memory contain data. When the processing circuitry requires access to the data at location X, the cache circuitry responds by moving a copy of the data from location X into the cache. Furthermore, when the processing circuitry requires access to the data at location Y, the cache circuitry responds by moving a copy of the data from location Y into the cache. If location X and location Y contain the same data, multiple copies of the same data will reside in the cache.
It should be understood that some computer architectures include multiple caches arranged in a hierarchical manner, i.e., a cache hierarchy having a series of cache levels. For example, some computer architectures utilize a Level 1 (or L1) cache and a Level 2 (or L2) cache in addition to a standard dynamic RAM cache. For such architectures, copies of data consumed by the processing circuitry typically migrate from the outermost level of storage, into the standard dynamic RAM cache, then into the Level 2 cache, and then into the Level 1 cache before reaching the processor. Similarly, for data written by the processing circuitry, copies of the data migrate from the Level 1 cache, then into the Level 2 cache, and then into the standard dynamic RAM cache before finally being stored into the outermost level of storage. If the processing circuitry consumes copies of the same data from two different locations of the outermost level of storage, or if the processing circuitry writes copies of the same data to two different locations of the outermost level of storage (e.g., locations X and Y), multiple copies of the same data move through each level of the cache hierarchy.